Enhanced trench isolation structure

ABSTRACT

An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.

BACKGROUND OF THE INVENTION

In the processing of semiconductor devices, dielectric isolation isincreasingly used rather than junction isolation for increasing thepacking density of resultant structures and for providing physicalseparation of dissimilar devices. Moreover, trench isolation is used,particularly with planarization techniques such as chemical-mechanicalpolishing (CMP), to provide for a small, yet very electrically effectivedielectric isolation region, and yet still affords a planar structurefor facilitating subsequent formation of fine-pitch interconnect lines.

Frequently, tetra-ethyl-ortho-silicate (TEOS) is the dielectric materialused to fill a trench previously etched into the surface of thesubstrate, and the surface of the TEOS trench is planarized with thesilicon substrate surface by chemical-mechanical polishing.

Referring to FIG. 1A, two trench isolation regions 102 are shown formedwithin a semiconductor substrate 100. An active area 103 (for laterformation of a device, such as a field effect transistor) is shownlocated between the two trench isolation regions 102. The surfaces(labeled as 105) of the trench isolation regions 102 are shown as havingbeen planarized with the surface (labeled as 104) of the active area103, as is well known in the art of trench formation.

The various etches used to clean the silicon surface in the active areas(such as active area surface 104) are also usually applied to the trenchisolation region surface 105. Because the etch rate of common trenchfill materials, such as TEOS, is frequently greater than the etch rateof various substrate materials (such as single crystal silicon), asignificant over-etching of the trench regions 102 occurs. Thisover-etching creates a recessed trench fill surface 106, as shown inFIG. 1B, which leads to degraded electrical performance of thedielectric isolation provided by the trench. Such degraded performanceincludes increased leakage currents along the edges of the recessed TEOStrench.

SUMMARY OF THE INVENTION

An improved method of trench isolation formation includes applying apolysilicon layer above a planarized trench, and converting thepolysilicon to oxide prior to etching the active areas. This convertedoxide is denser than the materials usually used to fill the trench, suchas TEOS, and results in less over-etching of the trench isolationregion. The quality of the dielectric isolation is consequentlyimproved, and in particular, less leakage current flows across thetrench isolation region. Moreover, less leakage current flows from asubsequently formed local interconnect layer.

In one embodiment of the present invention, a method of forming anintegrated circuit structure upon a semiconductor substrate having a topsurface includes forming a plurality of trench isolation regions, eachfilled with a trench dielectric material, at the top surface of thesemiconductor substrate, the trench isolation regions defining activearea regions therebetween; forming a protective layer over and fullycovering the trench isolation regions; and then removing materialoverlying the active area regions to expose the top surface of thesemiconductor substrate within the active area regions; wherein theprotective layer remains over the trench isolation regions during atleast a portion of the removing step to protect the trench isolationregions and to reduce removal of trench dielectric material during theremoving step; and then forming a gate dielectric layer on the exposedtop surface within the active area regions; and forming a gate electrodeover the gate dielectric layer within an active area region.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings.

FIGS. 1A-1B, labeled prior art, are a sequence of cross-sections of asemiconductor body illustrating the recessed trench which results fromover-etching a planarized trench isolation region during etching of theactive areas.

FIGS. 2A-2G are a sequence of cross-sections of a semiconductor bodyillustrating an improved semiconductor process flow, in accordance withone embodiment of the present invention, for creating a trench isolationregion.

FIGS. 3A-3D are a sequence of cross-sections of a semiconductor bodyillustrating an improved semiconductor process flow, in accordance withanother embodiment of the present invention, for creating a trenchisolation region.

The use of the same reference symbols in different drawings indicatessimilar or identical items.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Referring now to FIG. 2A, two trench isolation regions 102 are shownformed within a semiconductor substrate 100. Such a substrate 100 may bea wafer, an epitaxial layer formed upon a wafer, a re-crystallized layerformed upon a non-conductive layer or wafer, or any other suitablematerial in which devices are to be formed and isolation between devicesis desired. To form the trench isolation regions, a pad oxide layer 110is formed upon the surface of the substrate 100, either by deposition orby oxidation, and then a nitride layer 112 is formed, usually bydeposition, upon the pad oxide layer 110. Openings are defined withinthe nitride layer 112 by masking a photoresist layer (not shown) topattern the photoresist layer, then by etching nitride openingscorresponding to the locations where the trench isolation regions aredesired, using the patterned photoresist layer as a mask. Then, afterremoving the patterned photoresist layer, the patterned nitride layer112 is used as a mask to first etch the pad oxide layer 110 and then toetch the substrate 100, thereby creating trenches within the substrate100. After a brief oxidation to line the trench walls (not shown), thetrench is filled with, for example, TEOS, and then planarized using CMPto the top surface of the nitride layer 112. The resulting structure isshown in FIG. 2A. An active area 103 is shown located between two trenchisolation regions 102. The surfaces (labeled as 105) of the trenchisolation regions 102 are shown as having been planarized with thesurface of the nitride layer 112. The pad oxide layer 110 may be 20-100Å thick, while the nitride layer 112 may be 500-1500 Å thick.

Referring now to FIG. 2B, the remaining portions of the nitride layer112 are stripped from the surface, and then a variety of implants areperformed (collectively represented by implant 114) to provide forproper doping of the various active areas. Such implants 114 include,for example, a V_(T) (threshold) implant, a punch-through implant, andwell implants for both wells (e.g., for a CMOS process). The requiredphotoresist masking and the detailed process flows for such variousimplants is well known in the art, and is not discussed in detailherein.

Referring now to FIG. 2C, a polysilicon layer 118 is formed upon thesurface of the semiconductor body, which at this point in the processflow includes the surface 105 of the trench isolation regions 102, andthe surface of the remaining portions of the pad oxide layer 110. Thepolysilicon layer 118 is formed to a thickness of preferably 150-300 Å,by any of a variety of suitable polysilicon formation techniques, andmay be formed into an amorphous state if processed below about 580° C.,or may be formed into a poly-crystalline state if processed above about600° C. The polysilicon layer 118 is preferably formed by thedecomposition of silane gas, into which a gaseous source of nitrogen hasbeen added. If processed at about 620° C., the resultant deposition rateis approximately 40 Å per minute.

This polysilicon layer 118 is then converted into an oxide, preferablyin a manner resulting in nitrogen incorporated within at least the upperportion of the resultant oxide layer. For example, a source of nitrogenmay be provided within an oxidizing ambient used to convert thepolysilicon to oxide. Alternatively, nitrogen may be provided during afinal anneal of the formed oxide or by a plasma treatment of the oxide.In particular, the resultant oxide may be RTA annealed (i.e., “rapidthermal anneal”) in a nitrogen-bearing ambient (e.g., NO, N₂O, N₂, NH₃,or others) to incorporate nitrogen within the converted oxide. Theresultant structure is shown in FIG. 2D, which shows a converted polyoxide layer 120 now formed upon the remaining portions of the pad oxidelayer 110 and further upon the trench isolation regions 102.

The conversion of polysilicon layer 118 into the converted poly oxidelayer 120 results in a dense oxide directly on top of the trenchisolation regions. The addition of nitrogen into at least the upperportion of the converted poly oxide layer 120 results in a particularlyhigh-quality dense oxide above the active areas (e.g., active area 103)and above the trench isolation regions 102. Such a dense oxide etchesmore slowly than less dense oxides or other dielectrics, particularlyTEOS. Preferably a nitrogen-bearing layer is formed in at least theupper portion of the converted poly oxide layer 120 having a 3-5%concentration of nitrogen within the top 50 Angstroms of thenitrogen-bearing layer.

Continuing with the process flow, the converted poly oxide layer 120 isthen etched to expose the active area surface prior to gate oxidation.This high-quality, dense oxide layer 120 protects the trench isolationregions 102 from the over-etch effects of this “pre-gate” etch step whenapplied to the active areas. The actual top surface of the trenchisolation regions 102 is exposed to the etch only near the end of theetch step, rather than exposed entirely during the etch step. Referringnow to FIG. 2E, a gate dielectric layer 121 is formed on the exposedactive area surface, and then gate electrodes 122 are formed, typicallyby depositing and patterning a polysilicon layer, as is well known inthe art. An LDD implant 124 is then performed to create the shallowsource/drain regions laterally aligned to the gate electrodes 122. Theresulting structure is illustrated in FIG. 2F, which shows LDD regions130 formed in the active areas 103 within the substrate 100, and on bothsides of each gate electrode 122. Continuing with the process flow, aconformal layer 132 such as a silicon nitride layer (i.e., a “nitride”layer) may be applied to the exposed surfaces of the semiconductor body,and in particular, to the sides of the gate electrodes 122, to provide aself-aligning mask for the heavy source/drain implant 134. Such aconformal layer 132 may preferably be formed to a thickness of 100-300Å, and may alternatively be formed of silicon oxynitride (SiON) insteadof silicon nitride. As shown in FIG. 2G, deep source/drain regions 140are formed laterally aligned to the conformal layer 132 on the sides ofthe gate electrodes 122.

Additional processing steps may be incorporated to fabricate other typesof devices, and further to provide one or more electrical interconnectlayers for connecting the various devices into useful circuits. Suchsteps are outside the scope of this invention, are well known in theart, and are consequently not discussed in detail here.

FIGS. 3A-3D are a sequence of cross-sections of a semiconductor bodyillustrating another embodiment of the present invention, which followsin sequence beginning after FIG, 2C. Referring now to FIG. 3A, aphotoresist layer is deposited upon the polysilicon layer 118 andpatterned slightly larger than the trench isolation regions, so that thepolysilicon covering the trench isolation regions is itself covered andprotected by the patterned photoresist 150. The polysilicon layer isthen etched to expose the pad oxide 110 over the active areas 103,without subjecting the polysilicon over the trench isolation regions toany of the etchant.

The resulting structure is shown in FIG. 3B, which shows the pad oxide110 exposed over the large portion of the active area 103, and shows theformation of polysilicon “stripes” 152 still covering the trenchisolation regions 102. The patterned photoresist 150 is then removed toexpose the surface of the polysilicon stripes 152. An optional NH₃anneal may be performed to create a nitrided polysilicon surface of thepolysilicon stripes 152. Such an anneal may be advantageously performedat a temperature of 800-1000° C. for a time between 10-30 seconds. Theprocess flow continues with the removal of the exposed portions of thepad oxide layer 110 over the active areas 103. The resulting structureis shown in FIG. 3C, which shows the active area 103 ready for gatedielectric formation. The remaining portions of the pad oxide layer 110lie adjacent to the trench isolation regions 102, and both are protectedby polysilicon stripes 152.

At this point of the process flow a gate dielectric layer may be formedon the surface of the active areas 103. For example, an oxidation may beperformed to grow a 20 Å oxide 160 which provides the gate dielectricfor transistors to be later formed within the active areas 103. Such agate oxidation also converts to an oxide an upper portion (e.g., 10-20Å) of the polysilicon stripes 152 (also labeled as 160). The resultingstructure is shown in FIG. 3D. After formation of polysilicon gateelectrodes over the gate oxide 160 within the active areas 103 (notshown), an additional oxidation may be performed to convert theremaining portion of the polysilicon stripes 152 to an oxide.Alternately, since the polysilicon stripes 152 are “encased” in oxide,they may be left as unconverted polysilicon.

The above process sequences portray that portion of a semiconductorprocess flow relevant to and necessary to understand the presentinvention. Other details, such as formation of CMOS wells, selectiveimplants to achieve multiple transistor threshold voltages, plug viaformation, local interconnect, formation of the above within epitaxiallayers, and others, may be incorporated with the invention describedherein to achieve other useful structures.

The present invention achieves a dense oxide above the trench isolationregions which is more robust against leakage currents across the trenchisolation region.

Although only a small portion of a semiconductor body has been shown forpurposes of illustration, it is understood that in actual practice, manydevices are fabricated on a single semiconductor wafer as widelypracticed in the art. Accordingly, the invention is well-suited for usein an integrated circuit chip, as well as an electronic system includinga microprocessor, a memory, and a system bus.

Those skilled in the art will readily implement the steps necessary toprovide the structures and methods disclosed herein, and will understandthat the process parameters, materials, and dimensions are given by wayof example only and can be varied to achieve the desired structure aswell as modifications which are within the scope of the invention.

While the invention has been largely described with respect to theembodiments set forth above, the invention is not necessarily limited tothese embodiments. Variations and modifications of the embodimentsdisclosed herein may be made based on the description set forth herein,without departing from the scope and spirit of the invention as setforth in the following claims. For example, the invention is notnecessarily limited to any particular transistor process technology, orto any particular layer thickness or composition. Accordingly, otherembodiments, variations, and improvements not described herein are notnecessarily excluded from the scope of the invention, which is definedby the following appended claims.

What is claimed is:
 1. A method of forming an integrated circuit structure upon a semiconductor substrate having a top surface, said method comprising: forming a plurality of trench isolation regions, each filled with a trench dielectric material, at the top surface of the semiconductor substrate, said trench isolation regions defining active area regions therebetween; forming a protective layer over and fully covering the trench isolation regions and not in direct contact with the semiconductor substrate within the active area regions; and then exposing the top surface of the semiconductor substrate within the active area regions; wherein said protective layer remains over the trench isolation regions during at least a portion of the exposing step to protect the trench isolation regions and to reduce removal of trench dielectric material during the exposing step; and then forming a gate dielectric layer on the exposed top surface within the active area regions; and forming a gate electrode over the gate dielectric layer within an active area region; wherein the protective layer comprises a polysilicon layer.
 2. A method as recited in claim 1 wherein the polysilicon layer is formed over the entire surface of the semiconductor body.
 3. A method as recited in claim 1 wherein portions of the polysilicon layer overlying the active areas are removed prior to the gate dielectric layer forming step, while keeping the trench isolation regions fully covered by remaining portions of the polysilicon layer.
 4. A method as recited in claim 1 wherein the protective layer forming step comprises: depositing a polysilicon layer over and fully covering the trench isolation regions; and converting at least an upper portion of the polysilicon layer to a resultant dielectric layer overlying the trench isolation regions.
 5. A method as recited in claim 4 wherein the polysilicon layer is fully converted to form the resultant dielectric layer overlying the trench isolation region.
 6. A method as recited in claim 4 wherein the deposited polysilicon layer is deposited directly onto the trench dielectric material.
 7. A method as recited in claim 4 wherein the trench isolation material comprises TEOS.
 8. A method as recited in claim 4 wherein the converting step includes forming a nitrogen-bearing layer within an upper portion of the resultant dielectric layer.
 9. A method as recited in claim 4 wherein the converting step includes oxidation in a nitrogen-bearing ambient.
 10. A method as recited in claim 4 wherein the converting step includes a rapid thermal anneal in a nitrogen-bearing ambient.
 11. A method as recited in claim 10 wherein the nitrogen-bearing ambient includes NH₃.
 12. A method as recited in claim 4 wherein the polysilicon deposition step is performed in a nitrogen-bearing ambient.
 13. A method as recited in claim 4 wherein the converting step includes a plasma treatment in a nitrogen-bearing ambient to form a nitrogen bearing layer within the converted polysilicon layer.
 14. A method as recited in claim 8 wherein the resultant nitrogen-bearing layer is 3-5% nitrogen within the top 50 angstroms of the nitrogen-bearing layer.
 15. A method as recited in claim 3 wherein the remaining portions of the polysilicon layer covering the trench isolation regions extend onto the top surface of the active area regions.
 16. A method of forming an integrated circuit structure upon a semiconductor substrate having a top surface, said method comprising the steps of: forming a plurality of trench isolation regions at the top surface of the semiconductor substrate, said trench isolation regions filled with a trench dielectric material and defining active area regions therebetween; forming at least over the trench isolation regions a protective layer comprising a polysilicon layer at least partially converted to an oxide layer; and then exposing the top surface of the semiconductor substrate within the active area regions; and then forming a gate dielectric layer on the exposed top surface within the active area regions; forming a gate electrode over the gate dielectric layer within an active area region; and forming source/drain regions associated with the gate electrode which are electrically isolated from any portion of the protective layer which may remain over the trench isolation regions.
 17. The method as recited in claim 16 wherein the protective layer comprises a fully converted polysilicon layer.
 18. The method as recited in claim 16 wherein the protective layer forming step comprises forming a polysilicon layer over the entire surface of the semiconductor body.
 19. The method as recited in claim 16 wherein the exposing step comprises removing portions of the protective layer overlying the active area regions while keeping the trench isolation regions fully covered by remaining portions of the protective layer.
 20. The method as recited in claim 18 wherein the protective layer forming step further comprises: converting at least an upper portion of the polysilicon layer to form a resultant dielectric layer at least overlying the trench isolation regions.
 21. The method as recited in claim 20 wherein the converting step comprises fully converting the polysilicon layer to form the resultant dielectric layer at least overlying the trench isolation regions.
 22. The method as recited in claim 20 wherein the polysilicon layer is chemical-vapor deposited directly onto the trench dielectric material.
 23. The method as recited in claim 20 wherein the trench isolation material comprises TEOS.
 24. The method as recited in claim 20 wherein the converting step includes forming a nitrogen-bearing layer within an upper portion of the resultant dielectric layer.
 25. The method as recited in claim 20 wherein the converting step includes oxidizing the polysilicon layer in a nitrogen-bearing ambient.
 26. The method as recited in claim 20 wherein the converting step includes a rapid thermal anneal in a nitrogen-bearing ambient.
 27. The method as recited in claim 20 wherein the converting step includes a plasma treatment in a nitrogen-bearing ambient to form a nitrogen bearing layer within the converted polysilicon layer.
 28. The method as recited in claim 19 wherein, after the exposing step, the protective layer covering the trench isolation regions extends partially over the active area regions.
 29. A method of forming an integrated circuit structure upon a semiconductor substrate having a top surface, said method comprising: forming a plurality of trench isolation regions at the top surface of the semiconductor substrate, said trench isolation regions filled with a trench dielectric material and defining active area regions therebetween; forming a polysilicon layer over both active area regions and trench isolation regions; converting at least a portion of the polysilicon layer into an oxide layer at least overlying the trench isolation regions; and then etching the converted polysilicon layer and any remaining polysilicon layer which together overly the active area regions to expose the top surface of the active area regions; and then forming transistors within the exposed active area regions having drain/source terminals electrically isolated from any remaining polysilicon layer overlying the trench isolation regions.
 30. The method as recited in claim 29 wherein, after the etching step, the trench isolation regions remain covered by at least some portions of the polysilicon or converted polysilicon layer.
 31. The method as recited in claim 29 wherein the converting step comprises fully converting the polysilicon layer to form a resultant dielectric layer at least overlying the trench isolation regions.
 32. The method as recited in claim 29 wherein the polysilicon layer is chemical-vapor deposited directly onto the trench dielectric material.
 33. The method as recited in claim 29 wherein the trench isolation material comprises TEOS.
 34. The method as recited in claim 29 wherein the converting step includes forming a nitrogen-bearing layer within an upper portion of the resultant dielectric layer.
 35. The method as recited in claim 29 wherein, after the exposing step, the protective layer covering the trench isolation regions extends partially over the active area regions.
 36. A method of forming an integrated circuit structure upon a semiconductor substrate having a top surface, said method comprising: forming a plurality of trench isolation regions at the top surface of the semiconductor substrate, said trench isolation regions filled with a trench dielectric material and defining active area regions therebetween; forming a polysilicon layer on the surface of the substrate over the trench isolation regions and over; but not in direct contact with, the active area regions, converting the polysilicon layer into an oxide layer; and then etching the converted polysilicon layer overlying the active area regions to expose the top surface of the active area regions; and then forming a transistor gate dielectric layer on the exposed top surface within the active area regions; forming transistor gate electrodes over the gate dielectric layer within the active area regions.
 37. The method as recited in claim 36 wherein the polysilicon layer is formed in direct contact with the trench isolation material forming the trench isolation areas.
 38. The method as recited in claim 36 wherein the converted polysilicon layer over the trench isolation regions is fully removed by the etching step.
 39. The method as recited in claim 36 wherein at least a portion of the converted polysilicon layer over the trench isolation regions remains after the etching step.
 40. The method as recited in claim 36 wherein the polysilicon layer is chemical-vapor deposited directly onto the trench dielectric material.
 41. The method as recited in claim 36 wherein the trench isolation material comprises TEOS.
 42. The method as recited in claim 36 wherein the converting step includes forming a nitrogen-bearing layer within an upper portion of the resultant dielectric layer.
 43. The method as recited in claim 36 wherein, after the etching step, the converted polysilicon layer covering the trench isolation regions extends partially over the active area regions. 